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Thames Innovation Centre, 8th May Agenda - What makes the Embedded Masterclass unique is the quality of the presentations. Rather than being typical sales presentations, we strive to make sure that they are informative, entertaining and a productive use of your time. We ask 'real' engineers to present, and we ask them to address 'real' issues regarding the latest embedded technologies and the challenges faced by embedded engineers on a daily basis. This is your chance to meet with experts in the industry and explore how you can address future designs, develop better code, gain access to more powerful tools or simply find answers to current challenges. |
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09-00 - 10.00 : Tea/Coffee and Bacon Rolls - Meet Exhibitors 10.00 - 10.45 : Optimising Real-Time Systems - Why average case optimisations are not the same as worst case optimisations. 10.45 - 11.30 : An Introduction to the UML 2 Testing Profile, and its practical application for testing of embedded software applications 11.30 - 12.15 : Time Triggered Systems - Why ?, Where ? and How It's Best Done 12.15 - 01.15 : Buffet Lunch - Meet Exhibitors 01.15 - 2.00 : Harnessing the Power of Multi-DSP Processing within CPU based Embedded Systems 02.00 - 02.45 : Using Real-Time Linux 02.45 - 03.30 : When good architecture goes bad - and what to do about it! 03-30 - 4.30 : Tea/Coffee Break - Meet Exhibitors |
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10.00 - 10.45 : Optimising Real-Time Systems - Why average case optimisations Dr Guillem Bernat For reliable, embedded software, when we optimize its execution time, we are concerned not only with how long it takes "on average" to do something but with the need to optimize the worst case behaviour. An optimization that improves the average case, but makes the worst case slower typically has a negative impact on reliability since it is the long worst case time that will cause a budget overrun, deadline miss or other delays in the system. This presentation addresses how to understand the worst case timing behaviour of your software and how to optimize it. We will cover key aspects of real-time systems: finding worst case execution times (WCET) and the worst case path, and why WCET analysis is not the same as average execution time analysis. Practical issues of looking for the worst-case "hot-spots", identifying timing bugs and identifying and verifying optimization opportunities will be explained. The presentation uses the RapiTime tool from Rapita Systems, a powerful on-target worst case execution time analysis tool that uses advanced program analysis techniques and on-target testing for accurate timing analysis. Company background: RapiTime is successfully used in the Avionics, Automotive and Telecommunications markets. Recent work with BAE Systems on the performance analysis of the mission computer of the Hawk aircraft has earned Rapita one of the 2006 BAE Systems Chairman's awards.
10.45 - 11.30 : An Introduction to the UML 2 Testing Profile, and its practical application for testing of embedded software applications The UML Testing Profile defines a language for designing, visualizing, specifying, analyzing, constructing and documenting the artifacts of test systems. It is a test modeling language that can be used with all major object and component technologies and applied to testing systems in various application domains. This presentation will introduce the main concepts encapsulated by the UML Testing Profile, and demonstrate a practical application of the profile to support testing for embedded systems development. The presentation will explore how the UML Testing Profile can be used as the basis for the automatic generation of test architectures, the graphical specification of tests using UML concepts such as Sequence Diagrams and Activity diagrams, and the automatic running of tests in a model based environment.
11.30 - 12.15 : Time Triggered Systems - Why ?, Where ? and How It's Best Done Dr. Michael J. Pont In a time-triggered embedded system, we have one (and only one) interrupt enabled. This interrupt is usually linked to a timer, which will generate periodic “ticks”: these ticks will, in turn, drive an appropriate (often very simple) operating system. If you are used to developing systems using multiple interrupts, this approach to software development may sound a little crazy. During this talk, my job will be to argue that use of a TT approach not only results in systems which have highly predictable behaviour, but also tends to reduce development times, unit costs, maintenance effort. My overall goal will not be to argue that a TT approach is a perfect march for all embedded systems (it isn't). However, I will conclude by suggesting that – as you start your next project – you should ask yourself: “Should we use a TT architecture this time?” By the end of this talk, I think you might be surprised how often the answer is: “Yes”. About TTE Systems 12.15 - 01.15 : Buffet Lunch - Meet Exhibitors
At the Embedded Masterclass Enea will be presenting their dSPEED technology, a real time operating system based technology that enables quicker development of multi-DSP embedded systems. This presentation will discuss how this technology has now evolved into a full platform solution offering start up and configuration, error handling, monitoring and supervision, event notification, logging and trace, diagnostics and statistics, in field post mortem debug and a comprehensive suite of inter-process and network communications technologies. Whether the development is a radar system or a wireless base station, DSP's have an important role to play and this presentation will discuss how developers worldwide are harnessing the power of DSP's within embedded systems. Biography 02.00 - 02.45 : Using Real-Time Linux An overview of the capabilities of the hard real-time Linux kernel from a users' perspective. Biography: 02.45 - 03.30 : When good architecture goes bad - and what to do about it! Even the most flexible software system can suffer as fixes and changes are made to it over the years by an ever-changing team in response to ever-changing requirements. In this session we'll consider such changes and look at how they can erode a system's software architecture. We'll also look at some examples of software architecture erosion and will take pleasure in seeing the mess that others have ended up in. You'll also learn about some valuable practices that can be adopted to prevent or slow erosion so that your software systems don't end up being case studies for future deliveries of this talk. Biography: Mark is also editor of the Code Generation Network - a specialist web resource focussed on model-driven software development tools and technologies. In this capacity Mark is the main organiser of this year's A regular speaker at conferences such as ACCU, SPA and SPLC, Mark brings a unique perspective (and style) to the Embedded Masterclass. Visit Mark's blog - The Variation Point - where he writes mainly on software - for more information. 03-30 - 4.30 : Tea/Coffee Break - Meet Exhibitors
Thanks and best regards |
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