* See more details about the technologies that will be exhibited

A Faster , Better Development of A Graphical User Interface

This presentation will discuss how to develop your GUI/HMI solution with:
no graphics code to write or no generated code to optimise, compile & debug.

A GUI/MHI solution that is also reusable and truly portable across different processor and rtos requirements. The presentation will explore the detailed GUI/HMI requirements of real time, embedded systems, and address such issues as:

- The challenges in design of modern interfaces and instrument clusters which pose complex graphics issues - anti-aliasing, offscreen drawing, transparencies to name a few.
- Early proof of concept and functional high fidelity prototype with which stakeholders can interact, with much earlier refinement of usability issues.
- Integration with custom graphical elements prepared with graphics design tools to achieve a unique and corporate branding look and feel.

Tilcon Software Limited is the leading provider of graphical user interface
software tools for embedded systems and real-time applications. Tilcon's
Graphics Framework technology can dramatically simplify your GUI/HMI
development process and can deliver results 10X faster than current COTS
technology. Tilcon's technology is an end to end solution, from concept
(rapid prototyping and codeless simulation) to target. It is pre-integrated
with COTS/Custom OS and optimized for a wide range of embedded hardware
targets. www.sdcsystems.com/gui-development.htm

About the presenter: Ray Mak is the Director of Product Development at Tilcon Software, a leading provider of Graphical User Interface tools and embedded graphics software solutions located Ottawa, Ontario, Canada. He is responsible for the architecture, software development, product management, quality assurance, customer documentation, professional services and technical support.

Ray has over 18 years of industry experience in the high technology sector holding management, architecture and technical leadership roles in companies such as Ciena, Catena Networks, Newbridge Networks and Nortel. He has led large teams in the design and delivery of carrier-grade embedded real-time systems, initial product deployments, multi-site development and integration with third party products.Ray holds an Honours Bachelor of Mathematics in Computer Science from the University of Waterloo.

back to top>>

Middleware Uncovered - Getting to market fast
Enea's OSE Real Time Operating is deployed in 50% of the world's base stations and also in 50% of the world's 3G mobile phones.

With the ever increasing time to market demands on embedded software engineers it's now proving more efficient for engineers and project managers to look at buying in integrated platforms which contain Operating System, data management and middleware components and even pre-integrated hardware solutions.

Enea and its key partners are now offering pre-integrated packages that build on the many years of experience gained from working with leading OEM manufacturers such as Ericsson, Motorola, Nokia and Fujitsu.Enea's accelerator platforms allow development teams to concentrate on developing the application level software which is the area that allows companies to differentiate against its competitors.This presentation will focus on key the technologies that can be purchased pre-integrated and will be biased towards telecom networks infrastructure components. Presented by Joel White, UK Manager of Enea.

back to top>>

2 million Options Aren't Enough
A Daimler Chrysler executive has been quoted as saying that “ Two million options aren't enough (for the Maybach)” but demand for an increasing number of software variants makes life increasingly difficult for embedded developers in an already challenging environment.Demand for variants arises from several sources including:

The conventional approach to variant management is usually an ad hoc combination of methods such as modifying copied files ( clone-and-own ), configuration-management branching, language-level constructs such as if-defs and templates and build and / or installer scripts.

This session introduces variant management an emerging approach to managing the development of variants across the whole life cycle. Amongst other benefits, systematic variant management leads to lower development costs, improved product quality and improved traceability.

About the presenter :Mark Dalgarno, Lead Consultant of Software Acumen, has worked in the software industry for over twenty years at companies both large and small. During this time he has mainly worked in software product development at all levels from programmer to head of software development. In 2004 Mark started Software Acumen as a specialist provider of tools and services to manage system variants. Since March 2006 he has also been editor of the Code Generation Network. In this role he is also the organiser of Code Generation 2007 - a new practitioner event on code generation tools and technologies.Mark is a Member of the British Computer Society (BCS), a Chartered Engineer (IEE), and of ACCU and is also an active participant in the BCSSoftware Practice Advancement group. In his spare time he helps organise meetings of this group in Cambridge.

back to top>>

Increase The Performance of Your Code with Trace Analysis

See how you can track the operation of your code with cycle accurate timings; analyze cache hits, misses and victims, you can also measure power consumption by each task and function as well as many other options. Users have found they are achieving over 20% performance improvement using these results to optimize their system operation.

About the presenter: Richard Copeman is the Technical Manager for Lauterbach Ltd., a wholly owned subsidiary of Lauterbach GMBH, the world's leading supplier of debug tools. Richard is responsible for all technical aspects of the company's business in the UK and Ireland, including training, technical support, product testing and system configuration and integration. Richard has over 20 years experience in the embedded industry working with almost every 32-bit processor architecture and with a broad range of real-time operating systems.

back to top>>

Accelerate your FPGA Development Process

This presentation will discuss how you can accelerate your FPGA development by utilising powerful hardware development platforms, along with advanced simulator / emulator software.

We will introduce a new method of FPGA / ASIC design, which promises shorter development times and higher design security for lower costs, and will discuss issues including:
- SEmulation® - the link between Simulation and Emulation
- the step-by-step transfer of the functional blocks from the VHDL design in the simulator into the FPGA (hardware) which greatly accelerates the simulations driven by the existing testbench
- enabling the engineer to introduce external components into the simulation, via a “hardware in the loop” process.
- Utilising multi-FPGA prototyping boards efficiently for large gate count designs
www.sdcsystems.com/fpga-asic-development-tools.htm

About the presenter : Dieter Scheurer is MD of Gleichmann Research in Austria, a sister company of the MSC Gleichmann group in Germany. After his diploma at a South German University in 1976 he worked as a hardware and software developer in different companies. He then went on to worked 18 years as ASIC FAE for NEC Electronics in Germany. In 2002 he changed to the NEC distributor Gleichmann and opens the ASIC and FPGA Design Centre in Munich. The FPGA Design Centre offers customer solutions for 8-32 bit processor systems for ASIC and FPGA. In 2004 the company founded Gleichmann Research in Austria, where they research new, highly sophisticated and unconventional ideas for electronic development systems.

back to top>>

"How long does your software take to run?"

"...and how can I reduce it?" are key issues for embedded engineers.

Today, software timing analysis doesn't have to be guesswork. This seminar
addresses how to understand the timing behaviour of your software and how
to improve it. We will cover key aspects of real-time systems: finding
worst case execution times (WCET) and the worst case path, and why WCET
analysis is not the same as average execution time analysis. Practical
issues of looking for the worst-case "hot-spots", identifying timing bugs
and identifying and verifying optimisation opportunities will be explained.

The presentation discusses the RapiTime tool from Rapita Systems, a powerful on-target worst case execution time analysis tool that uses advanced
program analysis techniques and on-target testing for accurate timing
analysis.

back to top>>

Automating Hardware Acceleration of Embedded Systems

Integrating a system into a single FPGA device can bring many benefits -
flexibility, protection from obsolescence, reduced size and lower power
consumption. It is also possible to replace computationally intense
software functions with much higher performance hardware modules.
Hardware design software tools can assist with this but there is usually
still a lot of effort involved. This presentation will describe a new
tool called the c2H compiler. This tool compiles ANSI C functions,
generates functionally equivalent HDL and integrates the resulting
module into both the hardware and software design flows. This tool
enables designers to leverage the power of the FPGA hardware but still
maintain high levels of productivity.

About The presenter : Stefano J. Zammattio is a member of the Altera Technical Product Marketing team; he is responsible for the European embedded market and specialises in the Nios II processor and related tools. Having been involved in the electronics industry since 1987, he has engineered and lead many system design projects. Stefano holds a BSc in Physics and a MSc in Medical Electronics.